1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a driver circuit including a slew rate control circuit.
2. Description of Related Art
USB (Universal Serial Bus) interfaces are used with a wide range of peripheral devices. Examples of standard peripheral devices using USB interfaces include a mouse, a keyboard, a disk drive, a printer, and audio/video equipment.
In order to transfer highly reliable information through a USB interface, it is important to improve the quality of the waveform of signals to be transmitted to and received from a transceiver. When communications are conducted at full speed and low speed, for example, even if a power supply voltage for driving the transceiver fluctuates in a range of 3.0 V to 3.6 V, a voltage level at which a pair of differential output signals to be transmitted and received cross each other (hereinafter, referred to as “crossover voltage”) is required to meet specifications in a range of 1.3 V to 2.0 V.
FIG. 5 is a circuit configuration diagram showing a differential driver 4 and a constant current source TD for driving the differential driver 4, which is disclosed in Japanese Unexamined Patent Application Publication No. 2003-309460. The constant current source TD includes a constant current circuit TD1 and constant current transistors TrD1 to TrD4. The differential driver 4 includes drivers 4a and 4b. The drivers 4a and 4b output signals with inverted phases. Specifically, the differential driver 4 outputs differential input signals, which are received at input terminals DIN and DINB, as differential output signals from output terminals D+ and D− through the drivers 4a and 4b. 
The circuit configuration of the driver 4a provided in the differential driver 4 will now be described. The driver 4a includes transistors MP1 to MP4 which are P-channel MOS transistors, transistors MN1 to MN4 which are N-channel MOS transistors, and capacitors C1 and C2 which are mirror capacitors.
One end of the transistor MP1 is supplied with a power supply voltage VDD. The diode-connected transistor MP2 is disposed between another end of the transistor MP1 and one end of the transistor MN1.
The one end of the transistor MN1 is also connected to the gate of the transistor MP4 and one end of the capacitor C1. A reference potential VSS is applied to another end of the transistor MN1 through the constant current transistor TrD1. Further, the power supply voltage VDD is applied to one end of the transistor MP3 through the constant current transistor TrD2. The diode-connected transistor MN2 is disposed between another end of the transistor MP3 and one end of the transistor MN3.
The another end of the transistor MP3 is also connected to one end of the capacitor C2 and the gate of the transistor MN4. The reference potential VSS is applied to another end of the transistor MN3. The gates of the transistors MP1, MN1, MP3, and MN3 are connected together to receive a single end signal through the input terminal DIN.
The power supply voltage VDD is applied to one end of the transistor MP4. Another end of the transistor MP4 is connected to one end of the transistor MN4, another end of the capacitor C1, and another end of the capacitor C2. The reference potential VSS is applied to another end of the transistor MN4. In this case, the transistor MP4 and the transistor MN4 constitute an output circuit. That is, an output signal from the output circuit corresponds to an output signal of the driver 4a. 
As described above, the constant current source TD includes the constant current circuit TD1, which generates a predetermined constant current, and the constant current transistors TrD1 to TrD4. The constant current generated by the constant current circuit TD1 is applied to the gates of the constant current transistors TrD1 to TrD4. Thus, the constant current transistors TrD1 to TrD4 are driven.
As described above, the driver 4a includes the transistors MP1 to MP4, the transistors MN1 to MN4, and the capacitors C1 and C2. Meanwhile, the driver 4b includes transistors MP5 to MP8 which are P-channel MOS transistors, transistors MN5 to MN8 which are N-channel MOS transistors, and capacitors C3 and C4 which are mirror capacitors. The connection configuration of the driver 4b is the same as that of the driver 4a, so the description thereof is omitted.
As shown in FIG. 5, the driver 4a has a circuit configuration including the constant current transistors TrD1 and TrD2. As with the driver 4a, the driver 4b has a circuit configuration including the constant current transistors TrD3 and TrD4.
The constant current circuit TD1 includes transistors MP9, MP10, and MP14 which are P-channel MOS transistors, and a transistor MN9 which is an N-channel MOS transistor. The transistor MP9 and the transistor MP10 constitute a current mirror circuit. The source of the transistor MP9 and the source of the transistor MP10 are each connected to the power supply voltage VDD. The drain of the transistor MP9 is connected to the gate of the transistor MP9, the gate of the transistor MP10, the source of the transistor MP14, the gate of the constant current transistor TrD2, and the gate of the constant current transistor TrD4. The drain of the transistor MP14 is connected to the gate of the transistor MP14, the source of the transistor MN9, and the reference potential VSS. The drain of the transistor MP10 is connected to the drain and gate of the transistor MN9, the gate of the constant current transistor TrD1, and the gate of the constant current transistor TrD3.
An output current of the transistor MP10 is supplied to the transistor MN9. The transistor MP9 forms a current mirror circuit with the constant current transistor TrD2 and the constant current transistor TrD4. The transistor MN9 forms a current mirror circuit with the constant current transistor TrD1 and the constant current transistor TrD3. Thus, a current generated in the constant current circuit TD1 is supplied to the driver 4a and the driver 4b. 
In the case of the circuit shown in FIG. 5, however, the crossover voltage of the differential output signals (i.e., output signals from the output terminals D+ and D−) fluctuates depending on the power supply voltage VDD. That is, if the power supply voltage VDD fluctuates for some reason, a fluctuation range of the crossover voltage may not meet the design specifications such as the USB specification. Note that Japanese Unexamined Patent Application Publication No. 2003-309460 fails to disclose a variation in the crossover voltage due to a variation in the power supply voltage VDD.
The reason why the above problem arises will be described below. First, a description is given of the case where an input signal DIN of the driver 4a shown in FIG. 5 changes from H level to L level. It is assumed that a drive current flowing through the constant current transistor TrD2 is denoted by i15 and the feedback capacitance of the capacitor C2 is denoted by C2. In this case, the drive current i15 flows to cause electric charges to be stored in the capacitor C2, thereby controlling a voltage Vdp of an output signal D+. That is, the voltage Vdp can be represented by the following expression (1).Vdp=−(1/C2)∫i15dt  (1)Accordingly, the output signal D+ changes from H level to L level.
Next, a description is given of the case where the input signal DIN changes from L level to H level. It is assumed that a drive current flowing through the constant current transistor TrD1 is denoted by i14 and the feedback capacitance of the capacitor C1 is denoted by C1. In this case, the drive current i14 flows to cause the electric charges accumulated in the capacitor C1 to be discharged, thereby controlling the voltage Vdp of the output signal D+. Thus, the output signal D+ changes from L level to H level. Since the driver 4b has the same circuit configuration as the driver 4a, the output signal D+ of the driver 4a has a phase opposite to that of an output signal D− of the driver 4b. 
It is assumed herein that the ON-resistance of the transistor MP14 is denoted by RP14 and the gate-source voltage of the transistor MP9 is denoted by Vgs9. In this case, a current i18 flowing between the source and drain of the transistor MP14 can be represented by the following expression (2).i18=(VDD−Vgs9)/RP14  (2)
Note that the current i18 serves as a reference current of the current mirror circuit which is formed of the transistors MP9 and MP10 and the constant current transistors TrD2 and TrD4. Specifically, the current i15 corresponding to the current i18 flows through the constant current transistor TrD2 as a drive current of a predriver 4c. Further, a current i17 corresponding to the current i18 flows through the constant current transistor TrD4 as a drive current of a predriver 4d. 
The output current of the transistor MP10 serves as a reference current of the current mirror circuit which is formed of the transistor MN9 and the constant current transistors TrD1 and TrD3. Specifically, the current i14 corresponding to the output current of the transistor MP10 flows through the constant current transistor TrD1 as the drive current of the predriver 4c. Further, a current i16 corresponding the output current of the transistor MP10 flows through the constant current transistor TrD3 as the drive current i16 of the predriver 4d. 
In this case, when the power supply voltage VDD is high, the drive currents i14 to i17 increase. That is, the drive currents of the predrivers 4c and 4d increase. As a result, a slew rate (gradient of a signal waveform) of each of the output signals D+ and D− increases. Meanwhile, when the power supply voltage VDD is low, the drive currents i14 to i17 decrease. As a result, the slew rate of each of the output signals D+ and D− decreases.
Assuming that the capacitors C1 to C4, which are provided in the drivers 4a and 4b, the transistors MP1 to MP8, and the transistors MN1 to MN8 have the same characteristics, respectively, and that the drive currents i14 to i17 have the same current value, for example, the rise (rising edge) and fall (falling edge) of the output signal D+ have the same gradient. Similarly, the rise and fall of the output signal D− have the same gradient. This is because the drive currents are supplied through the same current path even when the power supply voltage VDD fluctuates. In this circuit configuration, the crossover voltage is high when the power supply voltage VDD is high, while the crossover voltage is low when the power supply voltage VDD is low. This poses a problem that, if the power supply voltage VDD fluctuates for some reason, the fluctuation range of the crossover voltage may not meet the design specifications such as the USB specification.